1. Field of the Invention
The present invention relates to a refresh circuit, and in particular, to a refresh control circuit that decreases power consumption.
2. Background of the Related Art
As shown in FIG. 1, a related art refresh control circuit includes a row address input buffer 1 for receiving an external address ExADD, an auto refresh mode decoder 2 for interpreting an externally inputted instruction signal to implement an auto refresh operation and generate a sequential address increase flag signal REF, and a self-refresh mode decoder 3 for interpreting an externally inputted instruction signal to perform a self-refresh operation and generate a sequential address increase flag signal SREF. An auto refresh counter 4 generates all word line address signals in a memory cell array 7, which is an object of the refresh operation, in the auto refresh mode, and a self-refresh counter 5 generates all word line address signals in the memory cell array 7, which is the object of the refresh operation, based on a self timer in the self-refresh mode. A row decoder 6 decodes address signals from the auto refresh counter 4, the self-refresh counter 5 and the external address signals ExADD.
As shown in FIG. 2, the auto refresh mode decoder 2 includes inverters INV21 and INV22 for sequentially inverting an external clock signal CLK, an inverter INV23 for inverting an output signal of the inverter INV22 (i.e., the inverted signal of the external clock signal CLK) and a NOR-gate NOR21 for combining control signals CSB, RASB, CASB and WE. A D flip-flop DFF21 is controlled by the external clock signal CLK and an inverted signal of the external clock signal CLK. Further, an output signal from the NOR-gate NOR21 is applied to an input terminal of the D flip-flop DFF21. A NAND-gate ND21 NANDs an output signal from the D flip-flop DFF21 and the inverted signal of the external clock signal CLK received from the inverter INV22, and an inverter INV24 inverts an output signal from the NAND-gate ND21 and outputs the flag signal REF.
As shown in FIG. 3, the self-refresh mode decoder 3 includes a self-refresh completion circuit EX for receiving a control clock signal CKE and an inverted signal of a setting signal SET (i.e., SETB) and outputting a completion signal FSB, a self-refresh start circuit EN, and a RS flip-flop RSFF31. The self-refresh start circuit EN receives the external clock signal CLK, the control clock signal CKE and the control signals CSB, RASB, CASB and WE and outputs a start signal FRB. The RS flip-flop RSFF31 receives a completion signal FSB of the self-refresh completion circuit EX through an S-input terminal and the start signal FRB of the self-refresh start circuit EN through an R-input terminal and outputs the flag signal SREF to the self-refresh counter 5.
The self-refresh completion circuit EX includes a delay unit DE31 for delaying the control clock signal CKE, and a NOR-gate NOR31 for combining an output signal from the delay unit DE31 and the inverted signal SETB of the setting signal SET, which always has a low value when applying an electric power. The NOR-gate NOR31 outputs the output signal FSB.
The self-refresh start circuit EN includes inverters INV31 and INV32 for sequentially inverting the external clock signal CLK and a first D flip-flop DFF31 controlled by output signals from the inverters INV31 and INV32 to receive the control clock signal CKE through an input terminal. A second D flip-flop DFF32 receives an output signal from the first D flip-flop DFF31 through an input terminal and is controlled by the output signals of the inverters INV32 and INV31. A delay unit DE32 for delaying an internal clock signal ICK, which is an output signal from the second D flip-flop DFF32. Inverters INV33 and INV34 sequentially invert an output signal from the delay unit DE32, and a NOR-gate NO32 combines an internal clock signal ICK output by the second D flip-flop DFF32 and an output signal from the inverter INV34 to output an output clock signal CKD3.
Inverters EV35 and INV36 are for sequentially inverting the external clock signal CLK, an inverter INV37 is for inverting an inverted signal of the external clock signal CLK, and a NOR-gate NOR33 is for combining the external control signals CSB, RASB, CASB and WE. A D flip-flop DFF33 is controlled by the external clock signal CLK and the inverted signal of the same and has an input terminal that receives an output signal of the NOR-gate NOR33. A NAND-gate ND31 NANDs an output signal from the D flip-flop DFF33 and the external clock signal CLK, and an inverter INV38 inverts an output signal from the NAND-gate ND31. A delay unit DE33 is for delaying an output signal SAR from the inverter INV38. A NAND-gate ND32 is for NANDing an output signal CKD3 from the NOR-gate NOR32 and an output signal SARD from the delay unit DE33.
The operation of the related art auto refresh circuit will now be described. In the self-refresh mode, since an internal address signal by which a refresh operation is performed is generated by a internal chip timer in the self-refresh counter is generated to perform a refresh operation, it is not recognized as a word line address by which a refresh operation is performed by an external memory controller. Therefore, after the self-refresh operation is completed, an auto refresh operation is performed based on an external refresh instruction with respect to the entire address signals for an address signal, which is not refreshed during a self-refresh operation.
Namely, as shown in FIGS. 4A through 4F, after a self-refresh operation completion signal is inputted, an auto refresh operation is performed by control signals CS, RAS, CAS and WE as shown in FIGS. 4C through 4F generated by a memory driving controller for each word line in a corresponding refresh cycle. At this time, assuming that the number of word lines of the memory cell being auto-refreshed is 4096, 4096 auto refresh instructions are applied from the memory driving controller, and the chip internal address is sequentially increased by the auto refresh counter of the chip to perform an auto refresh operation.
Here, in the self-refresh mode, the self-refresh entry and exit are determined by the states of the refresh instructions CS, PAS, CAS and WE and the control clock signal CKE.
As described above, the related art memory chip has various disadvantages. In the related art refresh control circuit, in a 4K refresh chip for example, the interpretation operations are performed 4096 times by the instruction decoder with respect to the external control signals. Therefore, the consumption of the current is increased.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.